Conventional semiconductor devices generally include a semiconductor substrate, usually a silicon substrate, and a plurality of sequentially formed dielectric interlayers such as silicon dioxide and conductive paths or interconnects made of conductive materials. The interconnects are usually formed by filling a conductive material in trenches etched into the dielectric interlayers. In an integrated circuit, multiple levels of interconnect networks laterally extend with respect to the substrate surface. The interconnects formed in different layers can be electrically connected using vias or contacts. A conductive material filling process of such features, i.e., via openings, trenches, pads or contacts, can be carried out by depositing a conductive material over the substrate including such features.
FIGS. 1A-1E exemplify a conventional electrodeposition method and apparatus. FIG. 1A illustrates a substrate 10 having an insulator layer 12 formed thereon. Using conventional etching techniques, features such as a row of small vias 14 and a wide trench 16 are formed on the insulator layer 12 and on the exposed regions of the substrate 10. Typically, the widths of the vias 14 may range from a few microns to sub-micron. The trench 16 shown in this example, on the other hand, is wide and has a small aspect ratio. In other words, the width of the trench 16 may be five to fifty times or more greater than its depth. In other applications, the width of the trenches may be comparable or even smaller than its depth.
FIGS. 1B-1C illustrate a conventional method for filling the features with copper material. FIG. 1B illustrates that a barrier/glue 18 or adhesion layer and a seed layer 20 are sequentially deposited on the substrate 10 and the insulator 12. In FIG. 1C, after depositing the seed layer 20, a conductive material layer 22 (e.g., copper layer) is partially electrodeposited thereon from a suitable plating bath or bath formulation. During this step, an electrical contact is made to the copper seed layer 20 and/or the barrier layer 18 so that a cathodic (negative) voltage can be applied thereto with respect to an anode (not shown). Thereafter, the copper material layer 22 is electrodeposited over the substrate surface using specially formulated plating solutions.
As shown in FIG. 1C, the copper material 22 completely fills the via 14 and is generally conformal in the large trench 16, because the additives that are used are not operative in large features. The Cu thickness t1 at the bottom surface of the trench 16 is about the same as the Cu thickness t2 over the insulator layer 12. As can be expected, to completely fill the trench 16 with the Cu material, further plating is required. FIG. 1D illustrates the resulting structure after additional Cu plating. In this case, the Cu thickness t3 over the insulator layer 12 is relatively large and there is a step s1 from the top of the Cu layer on the insulator layer 12 to the top of the Cu layer 22 in the trench 16. For IC applications, the Cu layer 22 needs to be subjected to CMP or other material removal process so that the Cu layer 22 as well as the barrier layer 18 on the insulator layer 12 are removed, thereby leaving the Cu layer only within the features 14 and 16. These removal processes are known to be quite costly. Methods and apparatus to achieve a generally planar Cu deposit as illustrated in FIG. 1E would be invaluable in terms of process efficiency and cost. The Cu thickness t5 over the insulator layer 12 in this example is smaller than the conventional case as shown in FIG. 1D, and the step height s2 is also much smaller. Thin copper layer in FIG. 1E may be removed by electro polishing, CMP or other methods.
The importance of overcoming the various deficiencies of the conventional electrodeposition techniques is evidenced by technological developments directed to the deposition of planar copper layers. For example, U.S. Pat. No. 6,176,992 to Talieh, entitled “Method and Apparatus for Electrochemical Mechanical Deposition” and commonly owned by the assignee of the present invention, describes in one aspect an electro chemical mechanical deposition technique (ECMD) that achieves deposition of the conductive material into the cavities on the substrate surface while minimizing deposition on the field regions by polishing the field regions with a pad as the conductive material is deposited, thus yielding planar copper deposits.
U.S. application Ser. No. 09/740,701 entitled “Plating Method and Apparatus that Creates a Differential Between Additive Disposed on a Top Surface and a Cavity Surface of a Workpiece Using an External Influence,” also assigned to the same assignee as the present invention, describes in one aspect a method and apparatus for plating a conductive material onto the substrate by creating an external influence, such as causing relative movement between a workpiece and a mask, to cause a differential in additives to exist for a period of time between a top surface and a cavity surface of a workpiece. While the differential is maintained, power is applied between an anode and the substrate to cause greater relative plating of the cavity surface than the top surface and therefore a planar deposit is obtained.
U.S. application Ser. No. 09/735,546 entitled “Method and Apparatus For Making Electrical Contact To Wafer Surface for Full-Face Electroplating or Electropolishing,” filed on Dec. 14, 2000 describes in one aspect a technique for providing full face electroplating or electropolishing. And U.S. application Ser. No. 09/760,757 entitled “Method and Apparatus for Electrodeposition of Uniform Film with Minimal Edge Exclusion on Substrate,” filed on Jan. 17, 2001 describes in one aspect a technique for forming a flat conductive layer on a semiconductor wafer surface without losing space on the surface for electrical contacts.
As mentioned above, after depositing copper into the features on the semiconductor wafer surface, an etching, an electro polishing or a chemical mechanical polishing (CMP) step may be employed. However, in such processes there are problems in removing conductive materials off the wafer surface uniformly and in a controllable manner. These processes planarize the resulting surface and remove the conductive materials off the field regions of the surface, thereby leaving the conductive materials only within the via and trench features of interest. In the electro dissolution process, which includes electrochemical etchings or “electroetching” and electropolishing both the material to be removed and a conductive electrode are dipped into a suitable electrolyte solution. Typically an anodic (positive) voltage is applied to the material with respect to the conductive electrode. With the applied voltage, the material is electrochemically dissolved and removed from the wafer surface.
To this end, in the semiconductor IC industry, there is a need for processes and apparatus that can remove materials in a uniform and controllable manner.